2+N+2 and 3+N+3 HDI PCB Stack-ups, Stacked vs Staggered Microvias

What Does HDI Order Mean in 2+N+2 and 3+N+3 PCB Stack-ups?

The term of “order” refers to the sequential build-up stages, each involving a separate lamination and laser-drilling cycle, rather than the PCB’s total layer count. 2+N+2 (also called Second-order) HDI uses two such stages; 3+N+3 (also called third-order) uses three.

Both the constructions are key to pushing routing density to its limits in today’s high-end precision PCBs.

Explore multilayer PCB manufacturing, custom stack-ups and impedance control.

Second-Order HDI PCB Construction: Staggered and Stacked Microvias

The HDI stack-up structure 2+N+2 requires two separate cycles of lamination, drilling, and plating to complete the blind and buried via structure. Typical configurations fall into two categories:

Staggered Microvias in 2+N+2 HDI PCBs

For our 2nd-order HDI, to ensure maximum manufacturability in high-volume production, JetH PCB suggests that it will be a priority to implement a staggered microvia architecture for the L1–L2 and L2–L3 layers. Because the hole centers are physically offset and non-overlapping, this design avoids complex stacked-via constraints, making it our most established 2nd-order HDI process.

As a Chinese PCB manufacturer with more than 15 years of HDI PCBs experience, we feel responsible for explaining the process behind that distinction.

Since staggered vias are drilled and laminated, they don't need to align on the same axis. This gives us much better alignment tolerance, as long as the pad size and clearance requirements are met.

Q: Where is the structure 2+N+2 HDI PCBs with staggered microvias typically applied?

A: You’ll typically find them in high-performance hardware, such as top-tier GPUs, AI accelerators, server mainboards, and gaming smartphones. If your design is pushing data through blazing-fast interfaces like DDR5 and PCIe 5.0, this architecture ensures your signal integrity stays rock-solid.

Reference cases

• HDI Construction Case Study
• GPU accelerator board design
• Constraint-driven PCB design

Third-Order HDI PCBs: 3+N+3 Build-up and Lamination Shrinkage Control

3+N+3, as the absolute peak of mainstream mass production, it takes three separate build-up passes of lamination, laser drilling, and plating. While standard designs can span L1–L4 (or custom-engineered spans like L1 to L5) to use stacked or staggered vias. However, anylayer tech lets you drop microvias between any adjacent pair of layers freely.

This is where top-tier HDI printed circuit boards manufacturer truly stand out. It all comes down to shrinkage control across three lamination cycles- managing material expansion and resin shrinkage through three lamination cycles. Keeping the cumulative offset locked within ±40 μm (and ≤ 15 μm per stage) is a high-wire act that standard 2+N+2 HDI PCB factories simply can’t land.

6-Layer 2+N+2 HDI Example: LDI and Dynamic Sectional Scaling Compensation

Take a 6-layer 2+N+2 stack-up as a classic example: The process sequence kicks off with L3–L4 buried vias in the core. The first build-up pass adds L2–L3 microvias, and the second pass completes the L1–L2 microvias on top. In order to keep every microvia dead center on its target pad across two press cycles, JetH PCB processed HDI by LDI (Laser Direct Imaging) paired with dynamic sectional scaling compensation. That leads 100% via-to-pad alignment and LDI with dynamic sectional scaling.

To handle this HDI stack-up 2+N+, JetH PCB enforces dynamic sectional scaling compensation to hold single-stage alignment within 15μm.

What are the process limits and performance advantages of 3rd-order HDI PCBs?

Process Control Limits for HDI PCB:

Must leverage LDI (Laser Direct Imaging) and plasma descum to reliably hit 0.05 mm microvias. Locks layer-to-layer registration within ±15μm, and applies micron-level pre-compensation for three-cycle lamination distortion—setting a yield barrier far beyond 2-build HDI.

Core Performance:

But the payoff is huge: you unlock 40% more routing real estate, clear tight 0.3 mm BGAs with ease, squeeze the total profile under 0.8 mm, and trim high-frequency signal loss by 20%.

For material and impedance requirements, explore our RF and microwave PCB manufacturing solutions.

Where are HDI PCBs with 3+N+3 structures typically applied?

Any build requiring terabit-level data throughput and minimal footprint:

• Flagship Mobile SoCs: Enables dense fan-out for application processor substrates.
• 5G AAU Transceivers: Protects RF signals from thermal and registration drift.
• Enterprise FPGA Boards: Clears multi-gigabit channels with tight 0.3mm BGA pitch.
• SATCOM Avionics: Squeezes maximum routing density into weight-restricted profiles.

How do 2-build and 3rd-order HDI PCBs compare in core specifications?

DFM Takeaway: Third-Order HDI, Sub-0.3 mm BGAs and Via-in-Pad Routing

DFM Takeaway:

Absolutely, if you're routing sub-0.3 mm BGAs, it remains the mandatory architecture for sub-0.3 mm fine-pitch BGAs due to three physical constraints:

1. Routing Density Cap: staggered vias in HDI 2+N+2 stucture can't handle full BGA pin escape at this density.
2. Forcing a 2-build approach pushes layer counts from 6 layers up to 10+ layers.
3. Via-in-Pad Advantage: 3rd-order stacked vias route directly in-pad, shrinking board size and slashing net system costs.